Tensilica’s Xtensa V processor is a configurable, extensible and synthesizable 32-bit RISC processor core based on Tensilica's patented Xtensa instruction set and architecture. It targets digital consumer, networking, office automation and wireless embedded SOC applications.
Xtensa V features include:
Xtensa Processor Architecture
5-stage high-performance pipeline
32-bit standard register widths and ALU
User-defined registers and execution datapaths up to 1024 bits
Instruction Set
Xtensa ISA – Patented
Compact 16/24b native instruction coding (no mode switch) delivers high code density with no performance penalty
Clock Speed
200 MHz in 0.18 micron process (worst case conditions)
300-350 MHz in 0.13 micron process (worst case conditions)
Performance
High performance base architecture
TIE (Tensilica Instruction Extensions)
Size
Approximately 25,000 gates – base processor
Power Consumption
0.4 mW/MHz in 0.18 micron process at 1.8V
0.1 mW/MHz in 0.13 micron process at 0.9V
According to Tensilica, a designer can use the Xtensa Processor Generator to automatically generate a tailored Xtensa V core. The designer can select from a broad selection of predefined standard RISC microprocessor features, options, and DSP engines and can add instructions and register extensions to the tailored processor. The Processor Generator then creates the complete processor solution set - processor hardware description in source RTL (Verilog or VHDL), plus supporting hardware implementation methodology scripts.
Use of this site is governed by our
Terms of Use
and Privacy Policy.
Except where otherwise specified, the contents of this site are copyright © 1999-2006
Ziff Davis Publishing Holdings Inc.
All Rights Reserved. Reproduction in whole or in part without permission is prohibited. Linux is a registered trademark of Linus Torvalds. All other marks are the property of their respective owners.
news feed