The Tensilica Xtensa LX is a configurable, extensible, and synthesizable processor core. Tensilica claims it provides I/O bandwidth, compute parallelism, and low-power optimization equivalent to hand-optimized, RTL-designed non-programmable hardware blocks. It targets traditional SOC embedded processor control tasks, as well as compute-intensive datapath hardware tasks.
Tensilica says that SoC designers can mold one or more Xtensa LX processors to an exact fit to the target task, using Tensilica's "processor generator" technology. The designer selects and configures predefined processor attributes and, using the Tensilica Instruction Extension (TIE) methodology, adds Verilog descriptions of execution datapaths, I/O ports, and registers to deliver performance, area, and power characteristics equivalent to custom logic design.
According to Tensilica, Xtensa LX features:
Lower power through automated insertion of fine-grain clock gating for every functional element of the Xtensa LX processor, including designer-defined functions. The minimum configuration dissipates 0.05 mW/MHz in a representative 130 nm process technology.
I/O throughput at RTL speeds - Designers can choose one or two 128-bit wide load/store units, add direct ports and queues, allowing the Xtensa LX processor to communicate as fast and flexibly as RTL blocks, Tensilica claims.
Outstanding compute performance - The Xtensa LX processor’s FLIX (Flexible Length Instruction Xtensions) architecture allows designers to pack multiple operations more efficiently into wider words, according to Tensilica.
Better interfaces to on-chip memories - Designers can select two additional clock cycles for memory access if required by the application.
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